9. Initialization Interface
VCCOk: When asserted*1, VCCOk indicates to the processor that the +5 volt power supply (Vcc) has been above 4.75 volts for more than 100 milliseconds (ms) and is expected to remain stable. The assertion of VCCOk initiates the reading of the boot-time mode control serial stream (described in Initialization Sequence, in this chapter).
ColdReset*: The ColdReset* signal must be asserted (low) for either a power-on reset or a cold reset. The clocks SClock, TClock, and RClock begin to cycle and are synchronized with the deasserted edge (high) of ColdReset*. ColdReset* must be deasserted synchronously with MasterClock.
Reset*: the Reset* signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for a cold reset, or synchronously to initiate a warm reset. Reset* must be deasserted synchronously with MasterClock.
ModeIn: Serial boot mode data in.
ModeClock: Serial boot mode data out, at the MasterClock frequency divided by 256 (MasterClock/256).
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