6.7 FPU Instruction Pipeline Overview

Instruction Execution Cycle Time

Unlike the CPU, which executes almost all instructions in a single cycle, more time may be required to execute FPU instructions.

Table 6-14 gives the minimum latency, in processor pipeline cycles, of each floating-point operation for the currently implemented configurations. These latency calculations assume the result of the operation is immediately used in a succeeding operation.

Table 6-14 Floating-Point Operation Latencies

(a) These operations are illegal.

(b) These operations are undefined.

Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96

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