6.7 FPU Instruction Pipeline Overview
Figure 6-9 FPU Instruction Pipeline
Figure 6-9 assumes that one instruction is completed every PCycle. Most FPU instructions, however, require more than one cycle in the EX stage. This means the FPU must stall the pipeline if an instruction execution cannot proceed because of register or resource conflicts.
Figure 6-10 illustrates the effect of a three-cycle stall on the FPU pipeline.
Figure 6-10 FPU Pipeline Stall
To lessen the performance impact that results from stalling the instruction pipeline, the FPU allows instructions to overlap so that instruction execution can proceed as long as there are no resource conflicts, data dependencies, or exception conditions. The following sections describe the timing and overlapping of FPU instructions.
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