6.4 -Floating-Point Formats

6. Floating-Point Unit

6.4 Floating-Point Formats

The FPU performs both 32-bit (single-precision) and 64-bit (double-precision) IEEE standard floating-point operations. The 32-bit single-precision format has a 24-bit signed-magnitude fraction field (f+s) and an 8-bit exponent (e), as shown in Figure 6-6.

Figure 6-6 Single-Precision Floating-Point Format

The 64-bit double-precision format has a 53-bit signed-magnitude fraction field (f+s) and an 11-bit exponent, as shown in Figure 6-7.

Figure 6-7 Double-Precision Floating-Point Format

As shown in the above figures, numbers in floating-point format are composed of three fields:

sign field, s

biased exponent, e = E + bias

fraction, f = .b1b2....bp-1

The range of the unbiased exponent E includes every integer between the two values Emin and Emax inclusive, together with two other reserved values:

Emin -1 (to encode xb1 0 and denormalized numbers)
Emax +1 (to encode xb1 and NaNs [Not a Number])

For single- and double-precision formats, each representable nonzero numerical value has just one encoding.

For single- and double-precision formats, the value of a number, v, is determined by the equations shown in Table 6-5.

Table 6-5 Equations for Calculating Values in Single and Double-Precision
Floating-Point Format

For all floating-point formats, if v is NaN, the most-significant bit of f determines whether the value is a signaling or quiet NaN: v is a signaling NaN if the most-significant bit of f is set, otherwise, v is a quiet NaN.

Table 6-6 defines the values for the format parameters; minimum and maximum floating-point values are given in Table 6-7.

Table 6-6 Floating-Point Format Parameter Values

Table 6-7 Minimum and Maximum Floating-Point Values

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