6.3 FPU Programming Model
Figure 6-4 shows the format of the Control/Status register, and Table 6-3 describes the Control/Status register fields. Figure 6-5 shows the Control/Status register Cause, Flag, and Enable fields.
Figure 6-4 FP Control/Status Register Bit Assignments
Table 6-3 Control/Status Register Fields 
Figure 6-5 Control/Status Register Cause, Flag, and Enable Fields
The bits in the Control/Status register can be set or cleared by writing to the register using a Move Control To Coprocessor 1 (CTC1) instruction. FCR31 must only be written to when the FPU is not actively executing floating-point operations; this can be ensured by reading the contents of the register to empty the pipeline.
The Cause bits are written by each floating-point operation (but not by load, store, or move operations). The Unimplemented Operation (E) bit is set to a 1 if software emulation is required, otherwise it remains 0. The other bits are set to 0 or 1 to indicate the occurrence or non-occurrence (respectively) of an IEEE 754 exception.
When a floating-point exception is taken, no results are stored, and the only state affected is the Cause bit.
There is no enable for Unimplemented Operation (E). Setting Unimplemented Operation always generates a floating-point exception.
Before returning from a floating-point exception, software must first clear the enabled Cause bits with a CTC1 instruction to prevent a repeat of the interrupt. Thus, User mode programs can never observe enabled Cause bits set; if this information is required in a User mode handler, it must be passed somewhere other than the Status register.
For a floating-point operation that sets only unenabled Cause bits, no exception occurs and the default result defined by IEEE 754 is stored. In this case, the exceptions that were caused by the immediately previous floating-point operation can be determined by reading the Cause field.
When a floating-point exception is taken, the flag bits are not set by the hardware; floating-point exception software is responsible for setting these bits before invoking a user handler.
As shown in Table 6-4, these bits specify the rounding mode that the FPU uses for all floating-point operations.
Table 6-4 Rounding Mode Bit Decoding
Generated with CERN WebMaker
Accessing the Control/Status Register
When the Control/Status register is read by a Move Control From Coprocessor 1 (CFC1) instruction, all unfinished instructions in the pipeline are completed before the contents of the register are moved to the main processor. If a floating-point exception occurs as the pipeline empties, the FP exception is taken and the CFC1 instruction is re-executed after the exception is serviced.IEEE Standard 754
IEEE Standard 754 specifies that floating-point operations detect certain exceptional cases, raise flags, and can invoke an exception handler when an exception occurs. These features are implemented in the MIPS architecture with the Cause, Enable, and Flag fields of the Control/Status register. The Flag bits implement IEEE 754 exception status flags, and the Cause and Enable bits implement exception handling.Control/Status Register FS Bit
When the FS bit is set, denormalized results are flushed to 0 instead of causing an unimplemented operation exception.Control/Status Register Condition Bit
When a floating-point Compare operation takes place, the result is stored at bit 23, the Condition bit, to save or restore the state of the condition line. The C bit is set to 1 if the condition is true; the bit is cleared to 0 if the condition is false. Bit 23 is affected only by compare and Move Control To FPU instructions.Control/Status Register Cause, Flag, and Enable Fields
Figure 6-5 illustrates the Cause, Flag, and Enable fields of the Control/Status register.Cause Bits
Bits 17:12 in the Control/Status register contain Cause bits, as shown in Figure 6-5, which reflect the results of the most recently executed instruction. The Cause bits are a logical extension of the CP0 Cause register; they identify the exceptions raised by the last floating-point operation and raise an interrupt or exception if the corresponding enable bit is set. If more than one exception occurs on a single instruction, each appropriate bit is set.Enable Bits
A floating-point exception is generated any time a Cause bit and the corresponding Enable bit are set. A floating-point operation that sets an enabled Cause bit forces an immediate exception, as does setting both Cause and Enable bits with CTC1. Flag Bits
The Flag bits are cumulative and indicate that an exception was raised by an operation that was executed since they were explicitly reset. Flag bits are set to 1 if an IEEE 754 exception is raised, otherwise they remain unchanged. The Flag bits are never cleared as a side effect of floating-point operations; however, they can be set or cleared by writing a new value into the Status register, using a Move To Coprocessor Control instruction.Control/Status Register Rounding Mode Control Bits
Bits 1 and 0 in the Control/Status register constitute the Rounding Mode (RM) field.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
