6.3 FPU Programming Model
Implementation and Revision Register, (FCR0)
The read-only Implementation and Revision register (FCR0) specifies the implementation and revision number of the FPU. This information can determine the coprocessor revision and performance level, and can also be used by diagnostic software.
Figure 6-3 shows the layout of the register; Table 6-2 describes the Implementation and Revision register (FCR0) fields.
Figure 6-3 Implementation/Revision Register
Table 6-2 FCR0 Fields
The revision number is a value of the form y.x, where:
- y is a major revision number held in bits 7:4.
- x is a minor revision number held in bits 3:0.
The revision number distinguishes some chip revisions; however, MIPS does not guarantee that changes to its chips are necessarily reflected by the revision number, or that changes to the revision number necessarily reflect real chip changes. For this reason revision number values are not listed, and software should not rely on the revision number to characterize the chip.
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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