6.3 FPU Programming Model
Floating-Point General Registers (FGRs)
The FPU has a set of Floating-Point General Purpose registers (FGRs) that can be accessed in the following ways:
- As 32 general purpose registers (32 FGRs), each of which is 32 bits wide when the FR bit in the CPU Status register equals 0; or as 32 general purpose registers (32 FGRs), each of which is 64-bits wide when FR equals 1. The CPU accesses these registers through move, load, and store instructions.
- As 16 floating-point registers (see the next section for a description of FPRs), each of which is 64-bits wide, when the FR bit in the CPU Status register equals 0. The FPRs hold values in either single- or double-precision floating-point format. Each FPR corresponds to adjacently numbered FGRs as shown in Figure 6-2.
- As 32 floating-point registers (see the next section for a description of FPRs), each of which is 64-bits wide, when the FR bit in the CPU Status register equals 1. The FPRs hold values in either single- or double-precision floating-point format. Each FPR corresponds to an FGR as shown in
Figure 6-2.
Figure 6-2 FPU Registers
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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