5.3 Processor Exceptions
The Interrupt exception occurs when one of the eight interrupt conditions is asserted. The significance of these interrupts is dependent upon the specific system implementation.
Each of the eight interrupts can be masked by clearing the corresponding bit in the Int-Mask field of the Status register, and all of the eight interrupts can be masked at once by clearing the IE bit of the Status register.
Processing
The common exception vector is used for this exception, and the Int code in the Cause register is set.
The IP field of the Cause register indicates current interrupt requests. It is possible that more than one of the bits can be simultaneously set (or even no bits may be set) if the interrupt is asserted and then deasserted before this register is read.
Interrupt exception processing is shown in Figure 5-17.
Servicing
If the interrupt is caused by one of the two software-generated exceptions (SW1 or SW0), the interrupt condition is cleared by setting the corresponding Cause register bit to 0.
If the interrupt is hardware-generated, the interrupt condition is cleared by correcting the condition causing the interrupt pin to be asserted.
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