5.3 Processor Exceptions
A Watch exception occurs when a load or store instruction references the physical address specified in the WatchLo/WatchHi System Control Coprocessor (CP0) registers. The WatchLo register specifies whether a load or store initiated this exception.
The CACHE instruction never causes a Watch exception.
The Watch exception is postponed if the EXL bit is set in the Status register, and Watch is only maskable by setting the EXL bit in the Status register.
Processing
The common exception vector is used for this exception, and the Watch code in the Cause register is set.
Watch exception processing is shown in Figure 5-17.
Servicing
The Watch exception is a debugging aid; typically the exception handler transfers control to a debugger, allowing the user to examine the situation.
To continue, the Watch exception must be disabled to execute the faulting instruction. The Watch exception must then be reenabled. The faulting instruction can be executed either by interpretation or by setting breakpoints.
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