5.3 Processor Exceptions
The Trap exception occurs when a TGE, TGEU, TLT, TLTU, TEQ, TNE, TGEI, TGEUI, TLTI, TLTUI, TEQI, or TNEI*1 instruction results in a TRUE condition. This exception is not maskable.
Processing
The common exception vector is used for this exception, and the Tr code in the Cause register is set.
The EPC register contains the address of the instruction causing the exception unless the instruction is in a branch delay slot, in which case the EPC register contains the address of the preceding branch instruction and the BD bit of the Cause register is set.
Trap exception processing is shown in Figure 5-17.
Servicing
The process executing at the time of a Trap exception is handed a UNIX SIGFPE/FPE_INTOVF_TRAP (floating-point exception/integer overflow) signal. This error is usually fatal.
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