-Soft Reset Exception

5.3 Processor Exceptions

Soft Reset Exception

Cause

The Soft Reset exception occurs in response to either the Reset* input signal or a Nonmaskable Interrupt (NMI)*1.

The NMI is caused either by an assertion of the NMI* signal or an external write to the Int*[6] bit of the Interrupt register.

This exception is not maskable.

Processing

Regardless of the cause, when this exception occurs the SR bit of the Status register is set, distinguishing this exception from a Reset exception.

The processor does not indicate any distinction between an exception caused by the Reset* signal or the NMI* signal.

An exception caused by an NMI can only be taken if the processor is processing instructions; it is taken at the instruction boundary. It does not abort any state machines, preserving the state of the processor for diagnosis.
An exception caused by assertion of Reset* performs a subset of the full reset initialization. After a processor is completely initialized by a Reset exception (caused by ColdReset* or Power-On), Reset* can be asserted on the processor in any state, even if the processor is no longer processing instructions. In this situation the processor does not read or set processor configuration parameters. It does, however, initialize all other processor state that requires hardware initialization (for instance, the state machines and registers), in order that the CPU can fetch and execute the Reset exception handler located in uncached and unmapped space. Although no other processor state is unnecessarily changed, a soft reset sequence may be forced to alter some state since the exception can be invoked arbitrarily on a cycle boundary, and abort any multicycle operation in progress. Since bus, cache, or other operations may be interrupted, portions of the cache, memory, or other processor state may be inconsistent.

In both the Reset* and NMI cases the processor jumps to the Reset exception vector located in unmapped and uncached address space, so that the cache and TLB contents need not be initialized to service this exception. Typically, the Reset exception vector is located in PROM, and system memory does not need to be initialized to handle the exception.

As previously noted, state machines interrupted by Reset* may cause some register contents to be inconsistent with the other processor state. Otherwise, on an exception caused by Reset* or NMI the contents of all registers are preserved, except for:

EW bit in the CacheErr register, which is reset to 0 (R4400 only)
ErrorEPC register, which contains the restart PC
ERL bit of the Status register, which is set to 1
SR bit of the Status register, which is set to 1
BEV bit of the Status register, which is set to 1
TS bit of the Status register, which is set to 0
PC is set to the reset vector 0xFFFF FFFF BFC0 0000

Soft reset exception processing is shown in Figure 5-16.

Servicing

The exception initiated by Reset* is intended to quickly reinitialize a previously operating processor after a fatal error such as a Master/Checker mismatch. The NMI can be used for purposes other than resetting the processor while preserving cache and memory contents. For example, the system might use an NMI to cause an immediate, controlled shutdown when it detects an impending power failure.

The exceptions due to Reset* and NMI appear identical to software; both exceptions jump to the Reset exception vector and have the Status register SR bit set. Unless external hardware provides a way to distinguish between the two, they are serviced by saving the current user-visible processor state for diagnostic purposes and reinitializing as for the Reset exception. It is not normally possible to continue program execution after returning from this exception, since a Reset* signal can be accepted anytime and an NMI can occur in the midst of another error exception.

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