5.3 Processor Exceptions
Reset Exception
Cause
The Reset exception occurs when the ColdReset**1 signal is asserted and then deasserted. This exception is not maskable.
Processing
The CPU provides a special interrupt vector for this exception:
- location 0xBFC0 0000 in 32-bit mode
- location 0xFFFF FFFF BFC0 0000 in 64bit mode
The Reset vector resides in unmapped and uncached CPU address space, so the hardware need not initialize the TLB or the cache to process this exception. It also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state.
The contents of all registers in the CPU are undefined when this exception occurs, except for the following register fields:
- In the Status register, SR and TS are cleared to 0, and ERL and BEV are set to 1. All other bits are undefined.
- Config register is initialized with the boot mode bits read from the serial input (see Figure 5-14).
- The Random register is initialized to the value of its upper bound.
- The Wired register is initialized to 0.
- The EW bit in the CacheErr register is cleared (R4400 only).
Reset exception processing is shown in Figure 5-14.
Servicing
The Reset exception is serviced by:
- initializing all processor registers, coprocessor registers, caches, and the memory system
- performing diagnostic tests
- bootstrapping the operating system
Copyright 1996, MIPS Technologies, Inc. -- 21 MAR 96
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