-Exception Vector Locations

5.3 Processor Exceptions

Exception Vector Locations

The Reset, Soft Reset, and NMI exceptions are always vectored to the dedicated Reset exception vector at an uncached and unmapped address. Addresses for all other exceptions are a combination of a vector offset and a base address.

The boot-time vectors (when BEV = 1 in the Status register) are at uncached and unmapped addresses. During normal operation (when BEV = 0) the regular exceptions have vectors in cached address spaces; Cache Error is always at an uncached address so that cache error handling can bypass a suspect cache.

Table 5-11 shows the 64-bit-mode vector base address for all exceptions; the 32-bit mode address is the low-order 32 bits (for instance, the base address for NMI in 32-bit mode is 0xBFC0 0000).

Table 5-12 shows the vector offset added to the base address to create the exception address.

Table 5-11 Exception Vector Base Addresses

Table 5-12 Exception Vector Offsets

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